The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, wafer level package based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. There may be two signal routing mechanisms in a wafer level package based semiconductor device, namely a fan-in signal routing mechanism and a fan-out signal routing mechanism. In a semiconductor device having a fan-in signal routing mechanism, input and output pads of each die are limited to an area within the footprint of the semiconductor die. With the limited area of the die, the number of the input and output pads is limited due to the limitation of the pitch of the input and output pads.
In a semiconductor device having a fan-out signal routing mechanism, the input and output pads of a die can be redistributed to an area outside the area of the die. As such, the input and output pads can spread signals to a larger area than the area of the die and provide additional space for interconnects. As a result, the number of input and output pads of the semiconductor device can be increased.
In a fan-out structure, the signal redistribution can be implemented by using a redistribution layer. The redistribution layer may couple an input and output pad within the area of the die and another input and output pad outside the area of the die so that signals from the semiconductor die can be spread outside the footprint of the semiconductor die.
A molding compound layer may be formed over the semiconductor die. The molding compound layer may be formed of epoxy based resins and the like. A portion of the molding compound layer located from the edge of the die to the edge of the semiconductor device is commonly referred to as a fan-out area of the semiconductor device.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.